1. Field of the Invention                The present invention relates to semiconductor devices and a method for fabricating the same, and more particularly, to semiconductor devices having a structure where an epitaxial silicon layer is formed in an active region and sources and drains are formed in the epitaxial silicon layer and a fabricating method of the same.        
2. Description of the Related Art
As semiconductor devices become more highly integrated, the design rule for the devices decreases. As a result, the areas allocated for forming semiconductor devices are also reduced, causing various problems in forming devices such as transistors. An NMOS transistor in a cell region having a memory device and PMOS and NMOS transistors in a peripheral region can secure electrical characteristics of transistors as long as a predetermined gate length is maintained in the transistors. When the devices are highly integrated, a short circuit can occur between source/drain junctions in a bulk region formed under channels, as well as a short channel effect, and the transistor devices may not operate properly.
To solve the above problems, various attempts have been made to increase the actual gate length of the transistor. One such attempt is a shallow junction method in which a shallow junction is formed to have a depth as shallow as possible.
However, as the devices have become more highly integrated and the design rule is extremely reduced, the distance between adjacent source and drain has become less than a critical value, even when the shallow junction method is used. When a thermal activation process, which is necessary during a junction formation process, is performed, impurity ions are diffused in a lateral direction. Consequently, junction areas are extended undesirably in the lateral direction. Accordingly, the distance between the sources and the drains becomes too narrow and source/drain junctions can be short-circuited.